The present invention relates to a power semiconductor device configured by a plurality of modules connected electrically in parallel, each module being configured by a power semiconductor switching element and a drive circuit for driving the switching element that are united into one.
Conventional semiconductor modules, when they do not incorporate none of a driving circuit and a protection circuit for a semiconductor switching element in them, are provided inevitably with a gate terminal, an emitter auxiliary terminal, etc. as disclosed in Japanese Patent Laid-Open No.59-100560, No.2-32560, No.10-14215, and No.10-173126. The gate terminal, the emitter auxiliary terminal, etc. are external terminals used to enter control signals and control voltages for driving, for example, transistors, IGBTs (Insulated Gate Bipolar Transistor), etc. required for configuring a semiconductor switching element.
On the other hand, an IPM (Intelligent Power Module) that incorporates a semiconductor switching element, a drive circuit for driving the switching element, and a protection circuit in itself enables an IGBT (Gate Drive Circuit) therein to receive a drive signal (input signal) via an input interface and a control logic as described, for example, in the technical trend of a high withstand voltage and large capacity power devices (Mitsubishi Denki Technical Report Vol.73, No.7, 1999, pp.7-11). The switching in the IPM is done by a drive voltage (gate voltage) applied to between the gate and the emitter of the IGBT from the gate drive circuit.
FIG. 5 shows a block diagram of a conventional IPM control protection circuit (Mitsubishi Denki Technical Report Vol.73, No.7, 1999, page 9).
As shown in FIG. 5, the conventional IPM is configured by a main circuit block that incorporates an IGBT in which a free wheel diode is connected between the collector and the emitter of an IGBT in the opposite direction, an output current control sensor is connected to the emitter, and a gate drive is connected to the base (gate), as well as a temperature sensor used to detect the ambient temperature of the IGBT in itself; a gate drive for controlling a gate signal output to the IGBT according to an IGBT output current control signal generated according to the current sensor detection signal and a current leading (di/dt) control signal; and a dedicated IC that incorporates a protection logic for controlling the gate signal so as to protect the IGBT according to the detection signal from the temperature sensor or power failure detector and a control logic for controlling the gate drive signal output to the gate drive according to an input signal entered from external via an input interface.
The IGBT of the IPM configured as described above, while the collector and the emitter are connected to external terminals of the module for connecting the main circuit therein, is not provided with any auxiliary terminal used for taking out the gate current and the emitter current directly. This is why no voltage can be applied directly to between the gate and the emitter of the IGBT.
This is because of the IPM function, which can omit both gate and emitter terminals otherwise to be used for driving and controlling the IGBT outside the module, since the IPM incorporates an IGBT drive circuit in itself.
Next, a description will be made for some problems to arise when a plurality of the conventional IPMs are connected in parallel for use.
When a plurality of IPMs are connected in parallel, common mode noise is eliminated by a common mode choke coil connected between ground lines of those IPMs and a drive signal is entered to each of the IPMs at the same time.
However, a difference occurs between the operation characteristics of those IPMs sometimes due to a time difference to occur between the IGBT drive circuits, a time difference to occur between turn-on and turn-off of each IGBT (hereinafter, to be referred to as a switching time), and a saturation voltage difference to occur between the collector and the emitter when the IGBT is on.
And, when a plurality of IPMs are connected in parallel, the total of an operation time difference between the drive circuits and an IGBT switching time difference between those IPMs causes a switching time difference between those IPMs.
Consequently, while a plurality of IPMs are connected in parallel, a difference between the turn-on times and a difference between turn-on voltages cause the current flowing in each of the IPMs connected in parallel to vary when in an IGBT on/off switching operation.
FIG. 6 shows a conventional method for connecting a plurality of semiconductor modules in parallel as disclosed, for example, in Japanese Patent Laid-Open No.10-14215. When the two IGBTs shown in FIG. 6 are different IGBT modules, a certain length is required for the gate connection line between the IGBT2A gate resistor 3A and the IGBT2B gate register 3B, thereby the line inductance becomes high.
Consequently, a resonance comes to occur in the resonance loop LP1 due to the gate-collector capacity of each of the gate connection line, the collector main circuit line CC, IGBT2A, and IGBT2B, as well as due to the gate-emitter capacity in each of the resonance loop LP2, the gate connection line, the emitter main circuit line EC, IGBT2A, and IGBT2B.
An IGBT module may be selected from those to be connected in parallel so that only the characteristics of the collector-emitter saturation voltage are adjusted in uniform between them. In the case of the conventional IPM parallel connection method as described above, it is required to adjust a plurality of such switching characteristics as the collector-emitter saturation voltage and the turn-on time or the turn-off time, etc. in uniform such so as to have a current flown in uniform in all the IPMs connected in parallel. This has been a problem for the parallel connection of IPMs as described above.
Furthermore, the conventional method has been confronted with another problem that a resonance occurs in the wiring loop of the gate auxiliary terminal connection line when the same voltage applies to between the gate and the emitter of the IGBT in each of the IPMs connected in parallel.
Under such circumstances, it is an object of the present invention to solve such the conventional problems and provide a power semiconductor device configured by a plurality of IPMs connected in parallel without selecting only the IPMs that are uniform in switching characteristics while such the selection has been required conventionally for parallel connection of IPMs.
In order to attain the above objects, the power semiconductor device of the present invention is formed as follows:
1. In the case when a first semiconductor switching circuit and a second semiconductor switching circuit which are configured by semiconductor switching elements respectively, are connected in parallel, first main electrodes at a main current input side are connected to each other and second main electrodes at the main current input side are connected to each other in each of the semiconductor switching elements, and one of a plurality of resistors having the same resistance value is connected to each of the second main electrodes and this resistor is connected to each of the second main electrodes by a first line conductor via an auxiliary terminal, and a control electrode of each of the semiconductor switching elements is connected by a second line conductor via an impedance element having a high impedance at a predetermined frequency.
2. Each semiconductor switching circuit of the present invention is an intelligent power module in which a semiconductor switching element, as well as a driver and a protection circuit of the switching element are united into one.
3. The first line conductor and the second line conductor are laid closely to each other.
4. The first line conductor and the second line conductor are configured by plate conductors disposed in parallel.
5. The first line conductor and the second line conductor are configured by twisted-pair lines formed by twisting a plurality of leads respectively.
6. The first line conductor and the second conductor are configured by shielded lines formed by sheathing a plurality of leads in a shielding member respectively.